• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Data information units are registered sequentially preparatory for transfer to two computer means, each by parallel-synchronous cooperation executing one of two accordant instruction sequences. The execution of each instruction sequence is divided in numbered periods which because of demanded information transfers comprise only one information transfer each. The demand for a transfer leads to a transfer number which is established by means of the period number obtained if the computer means execute instructions belonging to corresponding periods, and by means of the higher of the two period numbers if the instructions executed at the same time do not belong to corresponding periods. A transfer signal is transmitted to one of the computer means when the associated period number is equal to the transfer number. Due to a received transfer signal, the registered data information is transferred to the respective computer means. Thus the accordance of both instruction sequences is maintained in spite of a time displacement between corresponding periods.
    公开号:SU733525A3
    申请号:SU772555303
    申请日:1977-12-16
    公开日:1980-05-05
    发明作者:Леннарт Берг Эрик
    申请人:Телефонактиеболагет Л.М. Эрикссон (Фирма)；
    IPC主号:
    专利说明:

    one
    The invention relates to communication technology, can be used in data transmission systems.
    A device for transmitting discrete information is known, which contains an information buffer register, two processing units, to the information inputs of which are connected the outputs of the corresponding And 1 elements.
    However, such a device has low accuracy of information transfer.
    The purpose of the invention is to improve the accuracy of information transfer.
    To do this, a device for transmitting discrete information, containing an information buffer register, two data processing units, to the information inputs of which are connected the outputs of the corresponding AND elements, has been introduced two number counters, a signal signal generator, an information register, a memory block, a reversing switch, a common comparator , two auxiliary comparators and additional elements I. At the same time, one of the outputs of each data processing unit is connected to the
    the corresponding inputs of the common comparator, the first and second comparators and the reversing switch, to the other inputs of which are connected the outputs of the common comparator, and the output of the reversing switch through the first additional element AND, the memory block and the second additional element AND connected in series comparators. One of the outputs of the information buffer register is connected to one of the inputs of the third
    16 additional element And, to another input of which and to the other inputs of the first and second additional elements And connected the corresponding outputs of the generator signal of the tags f
    a & to the inputs of which are connected, respectively, another output of the information buffer register and other outputs of the first and second blocks of MF data processing, combined with one of the inputs of the corresponding AND elements, to the other inputs of which the output of the third additional element AND is connected via information
    -. register. oi
    The drawing shows a structural electrical circuit of the proposed device.
    The device contains information buffer register 1, data processing units 2.3., Elements 4.5, counters 6.7 numbers, generators 8 tag tags, information register 9, memory block 10, reversing switch 11, comparators iJ14, elements AND 15-19, clap 20,21
    The device works as follows.
    Signal-al transmission enters blocks 2,3. The Kokd transition command is distributed on a period boundary. Part of the data processing is performed by a sequence of commands as a transfer sequence or only by adding a transfer command between two sequences. The transmission signal that acts on the inputs of the blocks 2.3 during the transmission period T selects only one transmission command, the execution time of which is included in the transmission period T. The outputs of the blocks 2.3 are energized during the execution time tj for the transmission command. The indication pulses appear at each boundary of the period.
    These indication pulses are received using two counters 6.7, which have the same volume. When blocks 2,3 start working with parallel synchronous merging, counters 6.7 count the number of periods. Comparator 12 compares the numbers obtained with the help of counters 6, 7, and shows at any time whether blocks 2 execute two command sequences in corresponding or irrelevant periods. Comparator 12 is a conventional type. The reversing switch 11 is designed to connect the block 10 through the element 15 to the counters 6.7. While element 15 is in the excited (triggered) state, block 10 accumulates the number of counters 6.7 and stores the larger of the numbers received depending on whether two command sequences are executed in the corresponding or non-corresponding periods. Comparators 13 and 14 are conventional type kaparators, the output of which is excited when the input signals are equal.
    Buffer register 1 is a known backward store type (the first recorded word is read first). Portions of the information data entered into it at arbitrary points in time are stored as a buffer. The buffer register has an indication output, which is excited if at least one piece of information is stored. Parts of the information data are transmitted through the element
    And 17 to the information register and from it through the elements And 4.5 to blocks 2.3.
    The second input element And 15 is excited by the element And 16 only if the triggers 20,21 are in the same state. This first state is established when the execution of the command sequence begins and when the execution of the transfer command ends. In order to achieve this, the flip-flops 20 and 21 supply the first inputs that are energized by the falling edge and, together with the control inputs of the And 4.5 elements, are connected 5 to the outputs of the blocks 2 and 3.
    During parallel-synchronous combining, block 10 performs the following functions: provided that the transfer of the first piece of information to block 2 is completed and that the buffer register 1 stores the second piece of information data, the second piece of information data is stored in block 10, from which it is read using the elements AND 4,5, which are excited when parts of the blocks 2.3 execute the transmission command intended for this second part of the information.
    In connection with each entry in the information register 9, the element AND 16 goes into an unexcited state and remains un-excited for the time relating to the transfer operation, but is excited at least for a short time when the transfer ends . The output of AND 16 is used when applying its logical zeros as tag signals, which are related to
    0 registration in the information register 9 and control elements And 15,16. Consequently, the items of information transfer labels stop the transfer of counted numbers to block 10, the contents of which for the required
    5, the transmission operation (request) is indicated as the transmission number t. Using the element And 16, having an inverting input, the comparators 13 and 14 compare instantly read
    0 numbers that are obtained from counters 6.7 only for the transmission of the number, and thus two transmission signals are generated relating to the respective transmission operation, and
    5, blocks 2 and 3 independently of the relative phase shift receive the separately mentioned transmission signals during the execution period, which is determined by transferring the number t.
    The use of the proposed device guarantees the fastest transfer of operations, and the sequence. The commands for block 2, 3 remain independent of the asynchronism between
    five
    权利要求:
    Claims (1)
    [1]
    Claim
    A device for transmitting discrete information, containing an information 5 buffer register, two data processing units, to the information “inputs of which the outputs are connected * of the corresponding elements AND, which requires that, in order to 10 increase the accuracy of information transfer , two number counters, a label signal generator, an information register, a memory block, a reversing switch, a general comparator, two ^ 5 auxiliary comparators and additional AND elements are introduced, and one of the outputs of each data processing unit through the number counter is connected to the corresponding inputs of the common comparator, the first and second comparators and the reversing switch, the outputs of the common comparator are connected to the other inputs, and the output of the reversing switch is connected through the first connected additional element AND, the memory unit and the second additional element And connected to other inputs the first and second auxiliary comparators, one of the outputs of the information buffer register is connected to one of the inputs of the third additional element And, to the other input of which and the other inputs of the first and second additional elements AND are connected to the corresponding outputs of the label signal generator, the inputs of which are connected respectively to the other output of the information buffer register and other outputs of the first and second data processing units, combined with one of the inputs of the corresponding elements AND, to the other inputs of which the output of a third of its additional element Й is connected through the information register.
    类似技术:
    公开号 | 公开日 | 专利标题
    SU733525A3|1980-05-05|Digital data transmitter
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    SU763811A1|1980-09-15|Phase synchronization system
    SU1128254A1|1984-12-07|Priority device
    SU1144099A1|1985-03-07|Microprogram device for data input/output
    SU437072A1|1974-07-25|Firmware Control
    SU1095204A1|1984-05-30|Device for selecting features of recognized objects
    SU1166110A1|1985-07-07|Microprogram control unit
    SU1434542A1|1988-10-30|Counter
    SU474010A1|1975-06-14|Communication device in computing system
    同族专利:
    公开号 | 公开日
    NL7713910A|1978-06-20|
    AU515012B2|1981-03-12|
    IT1089170B|1985-06-18|
    FR2374693B1|1985-02-22|
    BR7708274A|1978-08-08|
    US4196470A|1980-04-01|
    FR2374693A1|1978-07-13|
    YU298177A|1982-10-31|
    CA1087747A|1980-10-14|
    SE397013B|1977-10-10|
    ES465171A1|1978-10-01|
    GB1565320A|1980-04-16|
    AU3130077A|1979-06-14|
    MX143306A|1981-04-13|
    HU177434B|1981-10-28|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
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    GB2340627B|1998-08-13|2000-10-04|Plessey Telecomm|Data processing system|
    DE19948099A1|1999-10-06|2001-04-19|Infineon Technologies Ag|Processor system, in particular a processor system for communication devices|
    US7287184B2|2003-09-16|2007-10-23|Rockwell Automation Technologies, Inc.|High speed synchronization in dual-processor safety controller|
    US8732247B2|2009-09-28|2014-05-20|Bjorn Michael Dittmer-Roche|System and method of simultaneous collaboration|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    SE7614222A|SE397013B|1976-12-17|1976-12-17|METHOD AND DEVICE FOR TRANSFERRING DATA INFORMATION TO TWO PARALLEL WORKING COMPUTER PARTS|
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